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29 November 2016

Attention to Authors

The Volume 1, Number 2, November 2016 issue of IJARCE has been published and hardcopies have been sent to authors. Notice that, arrival process of the hardcopies, to your addresses, will takes between 12 to 30 days depending on your country of origin.

 

10 October 2016

Attention to Authors

The Volume 1, Number 1, September 2016 issue of IJARCE has been published and hardcopies have been sent to authors. Notice that, arrival process of the hardcopies, to your addresses, will takes between 5 to 30 days depending on your country of origin.

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Performance Evaluation of MOSFET against CNTFET and GNRFET

Artical 10 ; volume1 ; number2 ; Page: 16-24 ; PDF Download

Authors

Rakesh Yadav Manjunath, Pallavi Venkatesh

1. Department of Computer Engineering, California State University, Fullerton, USA.

Abstract

As the CMOS technology is being scaled down further into the nanoscale, we are witnessing lot of short channel effects which are resulting in considerable deviation from its normal behavior. Also, the leakage current is increasing which is leading to power dissipation issues is small chips. Because of this many alternative technologies are being explored with an intent to replace the existing CMOS technology. Carbon Nanotube Field Effect Transistor (CNTFET) and Graphene Nanoribbon Field Effect Transistor (GNRFET) are among the technologies which are being widely studied and has been proposed to be a likely candidate to replace the MOSFET technology. In this paper, we have done extensive simulations on CNTFET and GNRFET, looking at how some of the device parameters affects the performance of the CNTFET and GNRFET. We have used the HSPICE and CosmosScope tools for the simulation and verifying the graphs. The CNTFET simulations were done using the model developed by the Stanford University and the GNRFET simulations using the HSPICE model developed by the University of Illinois. The next part of our research was concentrated on comparing the CNTFET and GNRFET with the MOSFET technology. The MOSFET technology was simulated by using the PTM models developed by the Arizona State University. Basic gate like inverter, NAND, NOR and XOR were built using all the three technologies for channel lengths 7nm, 10nm, 16nm and 32nm. The HSPICE and Cosmoscope were then used to find average dynamic power, delay, leakage powers, EDP and PDP in each case to compare between the different technologies. The results showed us that the CNTFET and GNRFET offers reduced power consumption when compared to the MOSFET and also operates at higher speed.

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